The advances of semiconductor manufacturing technology lead to continuous increase in the operating speed and decrease in the size of integrated circuits. An integrated circuit, comprising many electronic components such as transistors and capacitors, is typically formed by multiple levels with interconnects. Patterned conductive material on one level is electrically insulated from patterned conductive material on another level by an insulating layer made of dielectric material. Each level may include lines and patterns of various shapes and sizes. Different levels are vertically integrated and electrically connected with each other by structures often referred to as vias.
To increase the operating speed of integrated circuits while reducing power consumption, conductive material with a lower electrical resistance, such as copper, is used. However, copper is difficult to etch in a semiconductor environment. As a result, a damascene approach is used, which comprises etching trenches and vias in the insulating layer and subsequently filling the trenches and vias with conductive material, such as copper. Then the conductive material is polished down to the surface of the insulating layer by, for example, chemical mechanical polishing (CMP) to form the desired metal pattern. The damascene process is advantageous because: (1) it is easier to control the dimensions and registration of etched lines in the dielectric material than controlling the etching of lines in copper, and (2) it is easier to make a planar surface by polishing the copper than by planarizing the dielectric.
In a typical via-first sequence, a mask is used to etch a via through two layers of dielectric between conductor layers. Then a trench that is wider than the via is etched through the top one of the two layers. To prevent the trench-etching step from etching through the underlying etch stop (e.g., nitride) layer and eroding the conductive line beneath the via, a photoresist plug is inserted in the via before the trench is etched. The trench mask is aligned with the via and the trench is etched.
However, the introduction of the via plug creates a problem, which has been observed in 0.13 μm copper technology fabrication. If the photoresist plug is too low, a via facet occurs. The facet is a widening of the via at the top of the lower one of the two dielectric layers, caused by erosion of the via wall near the top of the lower layer. The facet is unacceptable, because, for example, it causes poor deposition of the TaN barrier layer and copper film in the trench. The facet problem can be improved by reducing the photoresist plug etch-back over-etch time. However, reducing the etch-back time can lead to a different problem: the via fence (or veil). The via fence consists of a ring of material projecting upwards out of the via above the lower dielectric layer. The fence defect is also unacceptable, because it also causes poor deposition of the TaN barrier layer and copper film in the trench.
Attempting to avoid formation of facets and fences has resulted in a very narrow plug etch-back window.